/RISC-V-Processor

Verilog implementation of multi-stage 32-bit RISC-V processor

Primary LanguageVerilog

RISC-V-Processor


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Open Source RISC ISA

Verilog implementation of 32-bit RISC-V processor!
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Table of Contents

About The Project

In this project we implement a 32-bit, RISC-V ISA based processor in verilog. The sub-modules that are used and their interaction with each other are shown in the following picture.



Output waveform using GTKWave:

Project Structure:

  • Each sub-unit that has been created has its own folder in root of the repository.
  • This sub-unit folder comprises of the modules used in that particular unit.
  • Additionally it consists of testbench and waveform used for testing and debugging those modules.
  • The final processor implementation is in the folder called "Processor".
  • This uses all the relevent units created individually and integrates them to give us our working processor.

Tools Used

iVerilog:

While there are many compilers for verilog present, not many of them are open source, and even fewer are robust, user-friendly and updated regularly. Icarus Verilog checks all boxes and can be learnt easily with this really helpful wiki setup for it.

GTKWave:

Another really powerful open source tool that was essential in building this project was GTKWave. It helps to view vcd and other waveforms. Really important for debugging and understanding if dependencies of different signals are as described by you.

Getting Started

This is an example of how you may give instructions on setting up your project locally. To get a local copy up and running follow these simple example steps.

Setting up instructions

Before we begin to run our processor we must initialize the instruction memory with the desired sequence of instructions that we want to execute. By default 8 instructions are included that will execute in that particular sequence of initialization.

Initializing the register file

In order to implement instructions we must have values in the register to act upon, these values can be initialized in the register file. By default each register is initialized to have a value the same as the register number - 1. Example: Register 14 will have value 13.

Running the processor

Once the above initializations have been done as desired, compile the file "Processor_tb.v" using iverilog using the following command:

  • compilation
iverilog -o gen-compiled "Processor_tb.v"

The above command generates a compile file named as "gen-compile". After compilation we can execute the compiled file using:

  • execution
vvp gen-compiled

Viewing waveform

  1. The waveform generated from testbench is named as "output_wave.vcd"
  2. Use GTKWave to view the waveform file
gtkwave output_wave.vcd

License

Distributed under the MIT License. See LICENSE for more information.

Project Link: https://github.com/ash-olakangal/RISC-V-Processor