FPGA implementation of a image filtering
Components
Filter Bank
filter bank chooser
Multiplier (with adder)
Efficient adder
Fifo_buffer_3
Cache memory
Zipper
Module zipper takes the filter output and trim it down to the range 0...255.
Controller
This module provides control signals as shown in the picture
This is a complex module that do a lot of calculationsEnabler
This module enable the controller after some time
Directory stucture
-
src
Contains the VHDL sources -
wcfg
Contains ISIM configurations -
src/test
Contains the VHDL test benches -
src/sims
Contains the VHDL test benches results