jz-huanng

jz-huanng's Stars

• ImagineAILab/ai-by-hand-excel

  1.4k191

• konrad-gajdus/miniMNIST-c

  Language:C1.1k110

• BrunoLevy/learn-fpga

  Learning FPGA, yosys, nextpnr, and RISC-V

  Language:C++2.6k245

• davidharrishmc/cvw

  Configurable RISC-V Processor

  Language:C213

• PyHDI/Pyverilog

  Python-based Hardware Design Processing Toolkit for Verilog HDL

  Language:Python634179

• ulixxe/usb_dfu

  Full Speed USB DFU interface for FPGA and ASIC designs

  Language:Verilog162

• iic-jku/SKY130_SAR-ADC1

  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

  Language:Verilog376

• splinedrive/kianRiscV

  RISC-V Linux SoC, marchID: 0x2b

  Language:C70147

• SpinalHDL/VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  Language:Assembly2.5k416

• bsc-loca/sauria

  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

  Language:SystemVerilog215

• strong-Ting/SingleCycle_RISC-V

  Language:Assembly1

• karpathy/llm.c

  LLM training in simple, raw C/CUDA

  Language:Cuda24.3k2.7k

• bnicola/DSPBox

  Language:Python304

• alex-matton/causal-transformer-decoder

  Language:Python724

• j1s1e1/VerilogPolarCodes

  Polar coding, decoding, and testing

  Language:SystemVerilog125

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k378

• luigifreda/slamplay

  slamplay is a collection of powerful tools to start playing and experimenting with SLAM in C++

  Language:C++38638

• jmahler/mips-cpu

  MIPS CPU implemented in Verilog

  Language:Verilog573185

• RossHartley/invariant-ekf

  C++ library to implement invariant extended Kalman filtering for aided inertial navigation.

  Language:C++460101

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.3k699

• analogdevicesinc/hdl

  HDL libraries and projects

  Language:Verilog1.5k1.5k

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k285

• mirkat1206/2021_Spring_NCTU_ICLAB

  NCTU 2021 Spring Integrated Circuit Design Laboratory

  Language:Verilog16737

• xxx-920/StabilizedPlatformSG90

  SG90稳定平台

  Language:C147

• jarzebski/Arduino-MPU6050

  MPU6050 Triple Axis Gyroscope & Accelerometer Arduino Library

  Language:C++432279

• patrick-kidger/diffrax

  Numerical differential equation solvers in JAX. Autodifferentiable and GPU-capable. https://docs.kidger.site/diffrax/

  Language:Python1.4k127

• TinyMPC/TinyMPC

  Model-predictive control for microcontrollers

  Language:C++57771

• open-sdr/openwifi

  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

  Language:C3.9k650

• jhshi/openofdm

  Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

  Language:Verilog373188

• neka-nat/cupoch

  Robotics with GPU computing

  Language:C++917107