jzuckerman

CS PhD student at Columbia University

Columbia UniversityNew York, NY

Pinned Repositories

BranchPredictor-
cs246-TAGE-predictor
Language:C++0 3 00
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog00
ecen5139_final_project
Language:Ada00
es100code
Language:Verilog00
esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Language:C40
help50
This is help50, a command-line tool that helps students understand error messages.
Language:Python00
MachSuite
Benchmarks for Accelerator Design and Customized Architectures
Language:C00
esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Language:C349 25 117107
esp-accelerator-templates
ESP Accelerator Templates
Language:C++5 7 07
esp-caches
SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
Language:C++17 8 06

jzuckerman's Repositories

jzuckerman/esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Language:C40
jzuckerman/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog00
jzuckerman/ecen5139_final_project
Language:Ada00
jzuckerman/es100code
Language:Verilog00
jzuckerman/help50
This is help50, a command-line tool that helps students understand error messages.
Language:Python00
jzuckerman/MachSuite
Benchmarks for Accelerator Design and Customized Architectures
Language:C00