/fpga_project

Primary LanguageVerilogMIT LicenseMIT

fpga_project

Description

processor.v contains the outline for a simple processor. A 16 bit model is used here. Separate modules for a State Machine, ALU, Multiplexer, Clock Dividor, and Registers have been built.

All modules are combined to form a processor in the Processor module. "netlist.pdf" shows the diagram of the connections of the processor.

"processor.v" is the top module for now.

Reference

Followed the guide on "reference.pdf".