- 8-bit Timer0 of ATMega328
- Verification Testbench for Timer0 of ATMega328
- 32-bit to 15-bit variable length FIFO
- Single Cycle MIPS (Can execute 23 instructions)
- Five Stage Pipelined MIPS (Can execute 23 instruction. Has a pipeline capable of forwarding and stalling)
- Root Mean Square Calculator
- 32-bit Multipliers (Iterative Architecture)
- N-bit Multipliers (Array Architecture, Iterative Architecture)
- Direct Form FIR Filter (Order = 8)
- Bus Arbiter (Support for 7 masters/7 slaves)
- IEEE754 compatible Natural Log Calculator
This project is licensed under GNU General Public License, version 3 (GPL-3.0)