This is an Ip design for AXI_Lite including master and slave in Vivado 2016.4
keqiao2017/AXI_Lite
This is an Ip design for AXI_Lite including master and slave in Vivado 2016.4
Verilog
This is an Ip design for AXI_Lite including master and slave in Vivado 2016.4
Verilog