Transactor doesn't properly send valid signals back to hvl

[kinap]

The valid signals go high at the appropriate clock cycle in the xactor, but the testOut structure doesn't have room for them. The top level test bench I don't think ever receives these values (they're always 0, not x, which is curious).

I was also seeing X's for expected data in the top level, but I didn't debug that enough to have confidence that it's not an artifact of another issue.

@pear7

[pear7]

The testOut structure wasn't large enough to accommodate the extra byte. This has been corrected. Additionally, the bytes were being read out the pipe in the wrong order.