kiranprasadk

kiranprasadk's Stars

• intel/systemc-compiler

  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

  Language:C++23534

• neovim/neovim

  Vim-fork focused on extensibility and usability

  Language:Vim Script80.4k5.5k

• ahkscript/awesome-AutoHotkey

  A curated list of awesome AutoHotkey libraries, library distributions, scripts, tools and resources.

  2.6k264

• intel/caffe

  This fork of BVLC/Caffe is dedicated to improving performance of this deep learning framework when running on CPU, in particular Intel® Xeon processors.

  Language:C++849491

• opencomputeproject/Project-Zipline

  Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

  Language:Verilog27746

• SpinalHDL/SpinalHDL

  Scala based HDL

  Language:Scala1.6k310

• datasciencescoop/Data-Science--Cheat-Sheet

  Cheat Sheets

  Language:TeX18.3k

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python978320

• offensive-security/kali-arm-build-scripts

  Kali Linux ARM build scripts

  872375

• offensive-security/nethunter-LRT

  The Nethunter Linux Root Toolkit is a collection of bash scripts which install Nethunter onto a supported device.

  30895

• offensive-security/kali-nethunter

  The Kali NetHunter Project

  3.4k888

• microsoft/MSRC-Security-Research

  Security Research from the Microsoft Security Response Center (MSRC)

  Language:Python1.3k160

• meganz/MEGAcmd

  Command Line Interactive and Scriptable Application to access MEGA

  Language:C++1.9k407

• bbcmicrobit/micropython

  Port of MicroPython for the BBC micro:bit

  Language:C596287

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.8k516

• VUnit/vunit

  VUnit is a unit testing framework for VHDL/SystemVerilog

  Language:VHDL703254

• greenblat/vlsistuff

  ideas and eda software for vlsi design

  Language:Python4411

• svunit/svunit

  Language:SystemVerilog17957

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala3.9k579

• esperantotech/boom-template

  A template for building new projects/platforms using the BOOM core.

  Language:Shell2421

• paszin/soundcloud_alexa_bridge

  use alexa to control your music played from an external device

  Language:Python293

• CMU-Perceptual-Computing-Lab/openpose

  OpenPose: Real-time multi-person keypoint detection library for body, face, hands, and foot estimation

  Language:C++30.5k7.8k

• riscv-boom/riscv-boom

  SonicBOOM: The Berkeley Out-of-Order Machine

  Language:Scala1.7k412

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.2k657

• ArchC/arm

  ARM processor model

  Language:C++27

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.7k491

• johnwickerson/memalloy

  Memory consistency modelling using Alloy

  Language:OCaml286

• apache/tvm

  Open deep learning compiler stack for cpu, gpu and specialized accelerators

  Language:Python11.5k3.4k

• d3/d3

  Bring data to life with SVG, Canvas and HTML. :bar_chart::chart_with_upwards_trend::tada:

  Language:Shell108k22.9k

• python-excel/xlrd

  Please use openpyxl where you can...

  Language:Python2.1k441