klcheungaj

klcheungaj's Stars

• fpgasystems/fpga-network-stack

  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

  Language:C++728258

• wengwz/blue-ethernet

  High-performance Ethernet components for FPGA implementation

  Language:Bluespec51

• WangXuan95/BSV_Tutorial_cn

  一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

  Language:Bluespec48741

• Naunter/BT_BlockLists

  Transmission block list

  Language:Shell93745

• mczerski/SD-card-controller

  WISHBONE SD Card Controller IP Core

  Language:Verilog11449

• AI4Finance-Foundation/ElegantRL

  Massively Parallel Deep Reinforcement Learning. 🔥

  Language:Python3.6k828

• openasic-org/xk264

  xk264：AVC/H.264 Video Encoder IP Core (RTL)

  Language:Verilog258

• UFund-Me/Qbot

  [🔥updating ...] AI 自动量化交易机器人(完全本地部署) AI-powered Quantitative Investment Research Platform. 📃 online docs: https://ufund-me.github.io/Qbot ✨ :news: qbot-mini: https://github.com/Charmve/iQuant

  Language:Jupyter Notebook6.9k924

• WangXuan95/FPGA-USB-Device

  An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

  Language:Verilog54789

• m1guelpf/auto-subtitle

  Automatically generate and overlay subtitles for any video.

  Language:Python1.4k231

• facebookresearch/fairseq

  Facebook AI Research Sequence-to-Sequence Toolkit written in Python.

  Language:Python30.1k6.4k

• Ayanaminn/N46Whisper

  Whisper based Japanese subtitle generator

  Language:Jupyter Notebook1.6k127

• XPixelGroup/HAT

  CVPR2023 - Activating More Pixels in Image Super-Resolution Transformer Arxiv - HAT: Hybrid Attention Transformer for Image Restoration

  Language:Python1.2k139

• xiaom233/BSRN

  Blueprint Separable Residual Network for Efficient Image Super-Resolution

  Language:Python16613

• swz30/CycleISP

  [CVPR 2020--Oral] CycleISP: Real Image Restoration via Improved Data Synthesis

  Language:Python49870

• NJU-Jet/SR_Mobile_Quantization

  Winner solution of mobile AI (CVPRW 2021).

  Language:Python14841

• limbo018/DREAMPlace

  Deep learning toolkit-enabled VLSI placement

  Language:C++663199

• jovton/USB-Storage-on-WSL2

  This article describes how you can access your USB storage device from Microsoft's Windows Subsystem for Linux 2 (WSL2)

  21222

• windowsair/wireless-esp8266-dap

  CMSIS-DAP compatible wireless debugger for various ESP chips such as ESP8266, ESP32. Optional 40MHz SPI acceleration, etc. 适配多种ESP芯片的无线调试器

  Language:C445226

• verilog-to-routing/vtr-verilog-to-routing

  Verilog to Routing -- Open Source CAD Flow for FPGA Research

  Language:C++998385

• Nic30/hdlConvertor

  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

  Language:C++27965

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.6k407

• antlr/grammars-v4

  Grammars written for ANTLR v4; expectation that the grammars are free of actions.

  Language:ANTLR10.1k3.7k

• vinceliuice/Matcha-gtk-theme

  Matcha is a flat Design theme for GTK 3, GTK 2 and Gnome-Shell

  Language:CSS75367

• vinceliuice/Qogir-icon-theme

  A colorful design icon theme for linux desktops

  Language:Shell73740

• andreisergiu98/arc-flatabulous-theme

  Arc theme with Flatabulous window controls.

  Language:CSS61142

• tonybaloney/Pyjion

  Pyjion - A JIT for Python based upon CoreCLR

  Language:C++1.4k59

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.7k500

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k663

• Qalculate/qalculate-gtk

  Qalculate! GTK+ UI

  Language:C++94068