Pinned Repositories
biriscv
32-bit Superscalar RISC-V CPU
Complete-Python-3-Bootcamp
Course Files for Complete Python 3 Bootcamp Course on Udemy
CS-IntroToAI
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Examples-in-book-write-your-own-cpu
《自己动手写CPU》一书附带的文件
HDL-FOR-ARM
libSTARK
A library for zero knowledge (ZK) scalable transparent argument of knowledge (STARK)
or1200
OpenRISC 1200 implementation
Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
risclite.github.io
klsllzx's Repositories
klsllzx/biriscv
32-bit Superscalar RISC-V CPU
klsllzx/Complete-Python-3-Bootcamp
Course Files for Complete Python 3 Bootcamp Course on Udemy
klsllzx/CS-IntroToAI
klsllzx/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
klsllzx/Examples-in-book-write-your-own-cpu
《自己动手写CPU》一书附带的文件
klsllzx/HDL-FOR-ARM
klsllzx/libSTARK
A library for zero knowledge (ZK) scalable transparent argument of knowledge (STARK)
klsllzx/or1200
OpenRISC 1200 implementation
klsllzx/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
klsllzx/risclite.github.io
klsllzx/learning_rust
klsllzx/riscv
RISC-V CPU Core (RV32IM)
klsllzx/riscv32-cpu-chisel
Learning how to make RISC-V 32bit CPU with Chisel
klsllzx/RTL-Contest
Concolic Testing on RTL for Detecting Security Vulnerabilities
klsllzx/speedtest-1
klsllzx/SuperScalar-RISCV-CPU
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
klsllzx/Verilog-caches
Various caches written in Verilog-HDL
klsllzx/verilog-doc
All About HDL
klsllzx/web_database_query_app
A web-based application that allows user to query a DB instance with a web interface
klsllzx/webdevbootcamp
All source code for back-end projects from the Web Developer Bootcamp