2v2 matrix inversion on CMOD A7 FPGA. Run with "vivado -source rebuild.tcl"
FP ALU code from: Grover, Naresh & Soni, M.K.. (2014). Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB. International Journal of Information Engineering and Electronic Business. 6. 1-14. 10.5815/ijieeb.2014.01.01.