DAQ-Algorithmn-to-FPGA Project
The goal of this project is to analyze detector data from the Stopping Target Monitor (STM) of the Mu2e experiment (https://mu2e.fnal.gov/) at Fermilab directly in hardware on the FPGA. The code is developed by Martin Voigt and Rober Ufer (Supervisors: Oliver Knodel and Stefan E. Müller) at the Helmholtz-Zentrum Dresden-Rossendorf (HZDR).
High Level Synthesis (HLS) is used to optimize the design process and allow non-HDL FPGA programming.
Presentation under Mu2e docdb-ID: 35505
System Architecture
The overall design process is more focused on a stand-alone hardware core and a test bench that simulates the flow of data into the core and validates the flow of data out of the core. A separate CPU on the system is not required or rather not utilized with the execution of the core itself.
All cores are implemented with Vivado HLS 2019.1.
The design is a pure streaming core using #pragma HLS pipeline and hls::stream<>.
Algorithms
Currently there are four algorithms:
| Algorithm | Implementation | README |
|---|---|---|
| Pulse Integratione Quality Analysis (original: Edge-finding Trigger by Jijun Chen, Shihua Huang, Dave Koltick) |
pulse_integration_quality_analysis_core.cpp: | README |
| Zero Suppression Cutout (original: Zero Suppression by Nam Tran) |
zero_suppression_cutout_core.cpp: | README |
| Moving Window Deconvolution (original: Moving Window Deconvolution by Nam Tran) |
MWD.cpp: | README |
| Simple Analysis and Cutout (original: Edge-finding Trigger by Jijun Chen, Shihua Huang, Dave Koltick) |
analysis_core.cpp: | README |