konradwilk

Maintainer of various subsystems in Linux kernel and in Xen project.

OracleBoston area

Pinned Repositories

asic-frequency_counter
Language:Verilog01
asic-setup-tools
Setup tools to install open source ASIC tools
Language:Makefile00
caravel_user_project
https://caravel-user-project.readthedocs.io
Language:Verilog10
eagle-libraries
00
fibonacci
Language:Verilog21
linux
Language:C2 1 04
sky130-chip-vis
Gate-level visualization generator for SKY130-based chip designs.
Language:Python11
swiotlb-test
Test module for SWIOTLB
Language:C1 1 00
wash-hand-pcb
Language:OpenSCAD1 1 00

konradwilk's Repositories

konradwilk/fibonacci
Language:Verilog21
konradwilk/linux
Language:C2 1 04
konradwilk/caravel_user_project
https://caravel-user-project.readthedocs.io
Language:Verilog10
konradwilk/sky130-chip-vis
Gate-level visualization generator for SKY130-based chip designs.
Language:Python11
konradwilk/swiotlb-test
Test module for SWIOTLB
Language:C1 1 00
konradwilk/wash-hand-pcb
Language:OpenSCAD1 1 00
konradwilk/asic-frequency_counter
Language:Verilog01
konradwilk/asic-setup-tools
Setup tools to install open source ASIC tools
Language:Makefile00
konradwilk/eagle-libraries
00
konradwilk/gdsii_misc
Language:Python00
konradwilk/open_mpw_precheck
konradwilk/openlane
NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
konradwilk/selinux-policy
selinux-policy for Fedora is a large patch off the mainline
konradwilk/sha1
Language:Verilog1 0
konradwilk/wash-hand-3d-box
1 0
konradwilk/xen
Xen repo
Language:C