Issues
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Correct spelling mistakes in projects
#54 opened - 0
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Rename dcache_unit to load_store_unit.
#52 opened - 0
Extend physical address space to 34 bits
#51 opened - 0
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Supporting of N extensions
#47 opened - 0
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Inference of memory block in BTB
#45 opened - 0
Imprecise instret register
#44 opened - 1
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Wrong fields name of xie register.
#41 opened - 0
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Add interrupt enable to UART module
#39 opened - 0
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Implement Hardware Performance Monitor
#37 opened - 1
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Reset mtime after timer interrupt taken
#35 opened - 0
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Simulator exit hints
#33 opened - 0
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Add FIFO to uart modules
#30 opened - 1
Enable Fast simulation
#29 opened - 1
Implement CSR field attributes
#28 opened - 0
CSR accessibility check mechanism
#26 opened - 0
Map mtime on read port of clint
#25 opened - 2
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Reconsider condition of interrupts
#23 opened - 1
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Prettify log format
#15 opened - 1
Simplify logic of data cache module
#14 opened - 1
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Refactoring debug signals
#10 opened - 0
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Implement CSR read, write with uimm
#8 opened - 0
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Lint check of the design
#4 opened - 1