Pinned Repositories
axi_bfm
DO NOT USE. Deprecated in favor of VUnit 3.0 AXI models
balena-sdk-python
Balena SDK for Python
configs
Version control of various configuration files
cs2-retakes
CS2 implementation of retakes. Based on the version for CS:GO by Splewis.
FreeCAD
This is the official source code of FreeCAD, a free and opensource multiplatform 3D parametric modeler. Issues are managed on our own bug tracker at https://www.freecadweb.org/tracker
freezing-spice
A pipelined RISCV implementation in VHDL
ghdl
VHDL 2008/93/87 simulator
VUnit-Tutorial
kraigher's Repositories
kraigher/axi_bfm
DO NOT USE. Deprecated in favor of VUnit 3.0 AXI models
kraigher/VUnit-Tutorial
kraigher/ghdl
VHDL 2008/93/87 simulator
kraigher/balena-sdk-python
Balena SDK for Python
kraigher/configs
Version control of various configuration files
kraigher/cs2-retakes
CS2 implementation of retakes. Based on the version for CS:GO by Splewis.
kraigher/FreeCAD
This is the official source code of FreeCAD, a free and opensource multiplatform 3D parametric modeler. Issues are managed on our own bug tracker at https://www.freecadweb.org/tracker
kraigher/freezing-spice
A pipelined RISCV implementation in VHDL
kraigher/interceptor
A pure Rust implementation of Pluggable RTP/RTCP processors
kraigher/language-server-protocol
Defines a common protocol for language servers.
kraigher/linguist
Language Savant. If your repository's language is being reported incorrectly, send us a pull request!
kraigher/lsp-types
Types for communicating with a language server
kraigher/matroska
A Rust library for reading Matroska (.mkv) files
kraigher/microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
kraigher/neorv32
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
kraigher/nvc
VHDL compiler and simulator
kraigher/OSVVM
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
kraigher/qmk_firmware
keyboard controller firmware for Atmel AVR USB family
kraigher/rustls-acme
kraigher/SigasiProjectCreator
Python scripts that help generating custom Sigasi Project and Libary configuration files
kraigher/stl_io
stl input and ouput for Rust
kraigher/UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
kraigher/webrtc
A pure Rust implementation of WebRTC