Pinned Repositories
academicpages.github.io
Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes
cse5522-project
CTTK
Constant-Time Toolkit
firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
Flute
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
kristinbarber
Config files for my GitHub profile.
kristinbarber.github.io
riscv-boom-firesim
kristinbarber's Repositories
kristinbarber/riscv-boom-firesim
kristinbarber/academicpages.github.io
Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes
kristinbarber/cse5522-project
kristinbarber/CTTK
Constant-Time Toolkit
kristinbarber/firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
kristinbarber/Flute
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
kristinbarber/kristinbarber
Config files for my GitHub profile.
kristinbarber/kristinbarber.github.io
kristinbarber/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
kristinbarber/riscv-pk
RISC-V Proxy Kernel
kristinbarber/riscv-tests
kristinbarber/sail-riscv
Sail RISC-V model
kristinbarber/sbox1-attack
kristinbarber/starter-academic
kristinbarber/Toooba
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT