kshitij-r

100-Days-of-RTL

100DaysOfRTL

100 Days of RTL

8x2-SRAM-Design

Project for EEE 5322 - VLSI Circuits & Technology

ahb3lite_wb_bridge

AHB3-Lite to Wishbone Bridge

AISS-Phase-III

AMBA_AXI_AHB_APB

AMBA bus lecture material

awesome-python

A curated list of awesome Python frameworks, libraries, software and resources

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

EEL-6763-Parallel-Computer-Architecture

Collection of assignments done in the course

USB-Keyboard-Driver---Character-Device-Driver

Project for EEL 5733 - Advanced Systems Programming

kshitij-r/8x2-SRAM-Design

Project for EEE 5322 - VLSI Circuits & Technology

kshitij-r/EEL-6763-Parallel-Computer-Architecture

Collection of assignments done in the course

kshitij-r/USB-Keyboard-Driver---Character-Device-Driver

Project for EEL 5733 - Advanced Systems Programming

kshitij-r/100-Days-of-RTL

kshitij-r/100DaysOfRTL

100 Days of RTL

kshitij-r/ahb3lite_wb_bridge

AHB3-Lite to Wishbone Bridge

kshitij-r/AISS-Phase-III

kshitij-r/AMBA_AXI_AHB_APB

AMBA bus lecture material

kshitij-r/awesome-python

A curated list of awesome Python frameworks, libraries, software and resources

kshitij-r/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

kshitij-r/Dynamic-Workload-Prediction-Tool

This tool is suitable for Trace driven simulation. It exploits parallel models such as MPI, OpenMP and CUDA

kshitij-r/SPARC

Specification and Analysis of Hardware-Software Interactions

kshitij-r/B-Plus-Tree

Project for COP 5536 - Advanced Data Structures

kshitij-r/basic_verilog

Must-have verilog systemverilog modules

kshitij-r/cppparser

A library to parse C/C++ source as AST

kshitij-r/EEL-5733---Advanced-Systems-Programming

Collections of assignments completed in the course

kshitij-r/elements_of_programming_interviews_python

Custom code for and solutions to problems from the book.

kshitij-r/FIFO_SystemVerilog_Assertion

Synchronous FIFO design & verification using systemVerilog Assertions

kshitij-r/gen_amba

AMBA bus generator including AXI, AHB, and APB

kshitij-r/klee

KLEE Symbolic Execution Engine

kshitij-r/kshitij.github.io

A webpage for all my projects

kshitij-r/minimal-risc-v-cpu

kshitij-r/pyuvm

The UVM written in Python

kshitij-r/Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

kshitij-r/riscv_soc

Basic RISC-V Test SoC

kshitij-r/SCR1

kshitij-r/SystemVerilogReference

training labs and examples

kshitij-r/Tomasulo-Simulator

Algorithm to simulate tomasulo algorithm. The algorithm shows step by step output.

kshitij-r/uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

kshitij-r/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog