/VHDL-precise-packet-generator

FPGA (Spartan 6 on Nexys3 board) precise packet generator in VHDL

Primary LanguageVHDLGNU General Public License v3.0GPL-3.0

VHDL-precise-packet-generator and RTT calculator

Precise packet generator is a simple precise network traffic generator that can measure round trip time. It's written in VHDL and designed targeting Spartan 6 on Nexys3 board but should work without any code modifications (other than replacing UCF file) on Nexys4 boards (with Artix 7).

See Wiki for full documentation!