Implementation of a hardware accelerator for image scaling and accompanying software, with comparison to software algorithm running on NiosII CPU. Developed in VHDL as part of a Digital VLSI Systems course. Find the detailed report here.
Implementation of a hardware accelerator for image scaling and accompanying software, with comparison to software algorithm running on NiosII CPU. Developed in VHDL as part of a Digital VLSI Systems course. Find the detailed report here.