lcbcFoo/ReonV

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

VHDLGPL-3.0

Issues

What is the frequency of this core?
#9 opened 3 months ago by shrimansoft
0
GRMON2 and RISCV
#5 opened 7 years ago by lcbcFoo
5
Linux compatibility
#8 opened 3 years ago by JOHNTBIJU
2
Running on modelsim
#7 opened 4 years ago by micheleportolan
0
ReonV on VC707
#6 opened 5 years ago by salmansheikh
0
Old signals from original SPARC ISA
#4 opened 7 years ago by lcbcFoo
0
Branch Prediction disabled/4 cycle branches
#1 opened 7 years ago by lcbcFoo
0
Trap and Exceptions
#3 opened 7 years ago by lcbcFoo
0
Big to Little Endian
#2 opened 7 years ago by lcbcFoo
1