Pinned Repositories
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AD7606
ara2
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
leo.github.io
openc910
OpenXuantie - OpenC910 Core
OpenVectorInterface
Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
riscv-isa-manual
RISC-V Instruction Set Manual
vortex
leoooo226's Repositories
leoooo226/leo.github.io
leoooo226/-
leoooo226/AD7606
leoooo226/ara2
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
leoooo226/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
leoooo226/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
leoooo226/openc910
OpenXuantie - OpenC910 Core
leoooo226/OpenVectorInterface
Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
leoooo226/riscv-isa-manual
RISC-V Instruction Set Manual
leoooo226/riscv-matrix-extension-spec
A matrix extension proposal for AI applications under RISC-V architecture
leoooo226/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
leoooo226/vortex
leoooo226/vroom
VRoom! RISC-V CPU