lgrativol

Ph.D student working on Federated Learning and embedded DNNs

IMT Atlantique

Pinned Repositories

cnn_vhdl_generator
AUTOMATIC VHDL GENERATION FOR CNN MODELS
Language:VHDL00
darknet-zynq
Accelerating DNN inference and training on Zynq
Language:C1 0 00
eusipco23_comp_fl
Language:Python00
fl_exps
Language:Python5 1 01
flocora_eusipco24
flocora - Eusipco 2024
Language:Python1 1 00
gb-research
Game Boy hardware research
Language:VHDL00
hls4ml
Machine learning on FPGAs using HLS
Language:C++00
simple_riscv
Language:VHDL0 1 00
SOTA-routine
SOTA routine for training CIFAR-10/CIFAR-100/ImageNet on standard ResNets
Language:Python0 0 00
tcc
Repositório TCC 2020: Lucas Grativol Ribeiro.
Language:VHDL00

lgrativol's Repositories

lgrativol/fl_exps
Language:Python5 1 01
lgrativol/darknet-zynq
Accelerating DNN inference and training on Zynq
Language:C1 0 00
lgrativol/flocora_eusipco24
flocora - Eusipco 2024
Language:Python1 1 00
lgrativol/cnn_vhdl_generator
AUTOMATIC VHDL GENERATION FOR CNN MODELS
Language:VHDL00
lgrativol/eusipco23_comp_fl
Language:Python00
lgrativol/gb-research
Game Boy hardware research
Language:VHDL00
lgrativol/hls4ml
Machine learning on FPGAs using HLS
Language:C++00
lgrativol/simple_riscv
Language:VHDL0 1 00
lgrativol/SOTA-routine
SOTA routine for training CIFAR-10/CIFAR-100/ImageNet on standard ResNets
Language:Python0 0 00
lgrativol/tensil
Open source machine learning accelerators
Language:Scala00
lgrativol/tetris
Language:Python0 1 00