CompArch Deliverable 2
Group 6: Yukun Su (260425096), Yang Zhou (260401719), Wei Sing Ta (260481021), Lena Hsieh (260424941)
Assembler Part
####Usage
Step1 : open the the 'Assembler/Assembler/src' folder in the Terminal/Command
Step2 : Use 'make' command to build project
Step3 : 'java Main ' For example: 'java Main fib.asm'
Step4 : The binary machine code stores in the 'bin_result.txt'
Processor Part
The 5 stages pipeline design has been implemented. The five stages are Fetch, Decode, Execute, Memory and Writeback stage. Each stage is connected by a buffer register which reacts according to the instruction pipeline.
DataMemory is stored in DataInit.dat while InstructionMemory is stored in Init.dat
The reference design for the implemented CPU can be found on page 427 (Fig 7.58) the reference textbook Digital Design and Computer Architecture (Harris & Harris). The circuit diagram can also be observed in included PipelinedFigure.png
Hazard and Forwarding are partially implemented using above-mentioned design. We faced several issues writing to DataMemory.. so please inspect the waveforms of our code when grading..
Working branching is not implemented.
Add all files to a ModelSim project and compile in autogenerated order. The main circuit is located in MIPSCPU.vhd and can be run via simulation (must force clock signal)