KeyError: 'Unresolved clock domain: "pix5x_o"'

[mithro]

When trying to build the HDMI2USB-litex-video video targets on the Nexys Video we get the following error;

 CC       boot-helper-lm32.o
 LD       firmware.elf
chmod -x firmware.elf
 OBJCOPY  firmware.bin
chmod -x firmware.bin
python -m litex.soc.tools.mkmscimg -f firmware.bin -o firmware.fbi
make[1]: Leaving directory `/home/travis/build/timvideos/HDMI2USB-litex-firmware/build/nexys_video_video_lm32/software/firmware'
ERROR:root:Available clock domains:
- clk100
- clk200
- data0_cap_read
- data0_cap_write
- data1_cap_read
- data1_cap_write
- data2_cap_read
- data2_cap_write
- eth_rx
- eth_tx
- eth_tx90
- fmeter
- hdmi_in0_pix
- hdmi_in0_pix5x
- hdmi_out0_pix
- hdmi_out0_pix5x
- pix1p25x
- pix5x_o
- pix_o
- sys
- sys4x
- sys4x_dqs
Traceback (most recent call last):
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/migen/migen/fhdl/verilog.py", line 327, in convert
    f.clock_domains[cd_name]
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/migen/migen/fhdl/structure.py", line 707, in __getitem__
    raise KeyError(key)
KeyError: 'pix5x_o'
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
  File "./make.py", line 143, in <module>
    main()
  File "./make.py", line 127, in main
    vns = builder.build(**dict(args.build_option))
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/builder.py", line 168, in build
    toolchain_path=toolchain_path, **kwargs)
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/soc_core.py", line 300, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/build/xilinx/platform.py", line 39, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/build/xilinx/vivado.py", line 212, in build
    v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/build/xilinx/platform.py", line 33, in get_verilog
    special_overrides=so, attr_translate=self.toolchain.attr_translate, **kwargs)
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/build/generic_platform.py", line 367, in get_verilog
    create_clock_domains=False, **kwargs)
  File "/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/migen/migen/fhdl/verilog.py", line 338, in convert
    raise KeyError("Unresolved clock domain: \""+cd_name+"\"")
KeyError: 'Unresolved clock domain: "pix5x_o"'
---------------------------------------------

See https://travis-ci.org/timvideos/HDMI2USB-litex-firmware/jobs/352035545

I'm guessing this has something to do with the split_mmcm stuff?

[mithro]

I'm guessing it should be hdmi_in0_pix5x or hdmi_out0_pix5x?

[mithro]

third_party/litevideo/litevideo/output/hdmi/s7.py:                i_CLK=ClockSignal("pix5x_o"), i_CLKDIV=ClockSignal("pix_o"),
third_party/litevideo/litevideo/output/hdmi/s7.py:                i_CLK=ClockSignal("pix5x_o"), i_CLKDIV=ClockSignal("pix_o"),
third_party/litevideo/litevideo/output/hdmi/s7.py:        self.clock_domains.cd_pix5x = ClockDomain("pix5x", reset_less=True)
third_party/litevideo/litevideo/output/hdmi/s7.py:            Instance("BUFG", i_I=mmcm_clk1, o_O=self.cd_pix5x.clk)
Binary file third_party/litevideo/litevideo/input/__pycache__/datacapture.cpython-36.pyc matches
Binary file third_party/litevideo/litevideo/input/__pycache__/clocking.cpython-36.pyc matches
third_party/litevideo/litevideo/input/clocking.py:        self.clock_domains.cd_pix5x = ClockDomain(reset_less=True)
third_party/litevideo/litevideo/input/clocking.py:            self.clock_domains.cd_pix5x_o = ClockDomain(reset_less=True)
third_party/litevideo/litevideo/input/clocking.py:                # pix5x clk
third_party/litevideo/litevideo/input/clocking.py:            Instance("BUFIO",i_I=mmcm_clk2, o_O=self.cd_pix5x.clk),
third_party/litevideo/litevideo/input/clocking.py:                Instance("BUFG", i_I=mmcm_clk2_o, o_O=self.cd_pix5x_o.clk), # was BUFIO...
third_party/litevideo/litevideo/input/datacapture.py:                i_CLK=ClockSignal("pix5x"), i_CLKB=~ClockSignal("pix5x"),
third_party/litevideo/litevideo/input/datacapture.py:                i_CLK=ClockSignal("pix5x"), i_CLKB=~ClockSignal("pix5x"),

[mithro]

targets/nexys_video/video.py:        self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix5x.clk, period_ns(5*pix_freq))
targets/nexys_video/video.py:            self.hdmi_in0.clocking.cd_pix5x.clk)
targets/nexys_video/video.py:        self.platform.add_period_constraint(self.hdmi_out0.driver.clocking.cd_pix5x.clk, period_ns(5*pix_freq))
targets/nexys_video/video.py:            self.hdmi_out0.driver.clocking.cd_pix5x.clk)
targets/nexys_video/video.py:        pix5x_counter = Signal(32)
targets/nexys_video/video.py:        self.sync.hdmi_in0_pix5x += pix5x_counter.eq(pix5x_counter + 1)
targets/nexys_video/video.py:        self.comb += platform.request("user_led", 2).eq(pix5x_counter[26])

[enjoy-digital]

Fixed via 9b4169d.

[mithro]

Looks like this fixed the nexys_video but the old netv2 target still appears to be broken?
https://travis-ci.org/timvideos/HDMI2USB-litex-firmware/jobs/352461388

[enjoy-digital]

Fixed with #22.