enjoy-digital

EnjoyDigitalFrance

Pinned Repositories

colorlite
Take control of your Colorlight FPGA board with LiteX/LiteEth :)
Language:Python91 10 812
litedram
Small footprint and configurable DRAM core
Language:Python362 24 163113
liteeth
Small footprint and configurable Ethernet core
Language:Python194 17 6482
litepcie
Small footprint and configurable PCIe core
Language:Python443 28 67109
litesata
Small footprint and configurable SATA core
Language:Python120 18 1633
litescope
Small footprint and configurable embedded FPGA logic analyzer
Language:Python158 16 2238
litesdcard
Small footprint and configurable SDCard core
Language:Python107 13 1233
litex
Build your hardware, easily!
Language:C2.7k 97 768528
pcie_screamer
PCIe Screamer - TLPs experiments...
Language:C155 18 1031
usb3_pipe
USB3 PIPE interface for Xilinx 7-Series
Language:Verilog178 29 2729

enjoy-digital's Repositories

enjoy-digital/litex
Build your hardware, easily!
Language:C2.7k 97 768528
enjoy-digital/litepcie
Small footprint and configurable PCIe core
Language:Python443 28 67109
enjoy-digital/litedram
Small footprint and configurable DRAM core
Language:Python362 24 163113
enjoy-digital/liteeth
Small footprint and configurable Ethernet core
Language:Python194 17 6482
enjoy-digital/litescope
Small footprint and configurable embedded FPGA logic analyzer
Language:Python158 16 2238
enjoy-digital/pcie_screamer
PCIe Screamer - TLPs experiments...
Language:C155 18 1031
enjoy-digital/litesata
Small footprint and configurable SATA core
Language:Python120 18 1633
enjoy-digital/litesdcard
Small footprint and configurable SDCard core
Language:Python107 13 1233
enjoy-digital/colorlite
Take control of your Colorlight FPGA board with LiteX/LiteEth :)
Language:Python91 10 812
enjoy-digital/liteiclink
Small footprint and configurable Inter-Chip communication cores
Language:Python51 11 618
enjoy-digital/litex-acorn-baseboard
LiteX development baseboards arround the SQRL Acorn.
Language:Python49 14 88
enjoy-digital/litejesd204b
Small footprint and configurable JESD204B core
Language:Python37 4 410
enjoy-digital/litex_rp2040_pmod_test
Test of a RP2040 PMOD attached to a LiteX SoC.
Language:Python21 4 12
enjoy-digital/xtrx_julia
XTRX LiteX/LitePCIe based design for Julia Computing
Language:C21 7 133
enjoy-digital/thunderscope
LiteX based FPGA gateware for Thunderscope.
Language:Python19 8 123
enjoy-digital/litex_verilog_axi_test
Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
Language:Python13 5 25
enjoy-digital/litex_hw_ci
LiteX Hardware CI tests.
Language:Python6 4 16
enjoy-digital/openFPGALoader
Universal utility for programming FPGA
Language:C++5 0 01
enjoy-digital/litex_soc_gen_test
Test of LiteX standalone SoC generator.
Language:Python4 3 11
enjoy-digital/litepcie_ptm_test
LitePCIe PTM support / test repo.
Language:Python3 6 111
enjoy-digital/vhdl2doc
Language:JavaScript3 2 0
enjoy-digital/acorn_pcie_compute_test
PCIe compute test on Acorn CLE 215+.
Language:Python1 4 0
enjoy-digital/corescore
CoreScore
Language:Verilog1 2 0
enjoy-digital/LimeSuite
Driver and GUI for LMS7002M-based SDR platforms
Language:C1 1 0
enjoy-digital/litex_mister_test
Simplification test of MiSTer with LiteX to try to help/contribute to MiSTeX project.
Language:Verilog1 3 91
enjoy-digital/openocd
Spen's Official OpenOCD Mirror (no pull requests)
Language:C1 2 01
enjoy-digital/FASTSCOPE
Language:Python0 0
enjoy-digital/litex_64bit_addressing_test
Test/PoC of 64-bit addressing in LiteX.
Language:Python2 4
enjoy-digital/litex_verilog_axis_test
Integration test of Verilog AXI Stream modules (https://github.com/alexforencich/verilog-axis) with LiteX.
Language:Python3 0
enjoy-digital/openfpga-pong
FPGA Pong implementation, specifically for the Analogue Pocket
Language:Verilog0 0