enjoy-digital/liteeth

Issues

• Updating `liteeth` PyPI package?

  #159 opened 2 months ago by fischermoseley
  4

• mdio writes in udp config

  #156 opened 4 months ago by ameetgohil
  1

• Unable to simulate generated liteeth core

  #155 opened 4 months ago by ameetgohil
  2

• Packets are not received

  #154 opened 5 months ago by JochiSt
  0

• How do I add Ethernet support for Xilinx ZCU104?

  #153 opened 7 months ago by ratzupaltuff
  5

• Liteeth does not transmit out UDP packets with length 16

  #152 opened 7 months ago by rowanG077
  3

• ECP5 / RGMII doesn't meet timing closure

  #27 opened 4 years ago by ximinity
  9

• Question : Compatibility with XC7S25 Spartan-7 for SGMII core

  #150 opened 8 months ago by PJfixer
  3

• IP header contains null destination address

  #147 opened 8 months ago by jrsa
  5

• HSGMII/QSGMII PHYs support for 2.5GBASE-T/5GBASE-T

  #144 opened 10 months ago by ohault
  0

• ARP table improvements

  #140 opened a year ago by rowanG077
  0

• Is it possible to generate generic Liteeth Verilog?

  #130 opened a year ago by PedroAntunes178
  1

• LiteEthPHYMII vs LiteEthPHYGMII question

  #131 opened a year ago by roryt12
  0

• subtle difference between `s7rgmii` and `ecp5rgmii` phy implementations?

  #123 opened a year ago by gsomlo
  3

• When liteeth core is under reset it transmit out stale packets

  #129 opened a year ago by rowanG077
  1

• empty UDP packets and with content larger then 1472 bytes crashes core

  #128 opened a year ago by rowanG077
  0

• Custom RMII PHY PMOD question

  #125 opened a year ago by machdyne
  2

• Regression with Etherbone/LiteScope and PacketFIFO?

  #86 opened 3 years ago by enjoy-digital
  6

• Generation of verilog files???

  #117 opened 2 years ago by dipal004
  1

• Ethernet connection via switch

  #108 opened 2 years ago by lapnd
  1

• Standalone core generator does not work for ECP5

  #32 opened 4 years ago by ximinity
  17

• Add options to set link speed and duplex status manually

  #109 opened 2 years ago by romanetz
  0

• RX Broadcast breaks Etherbone communication

  #107 opened 2 years ago by duqiang
  1

• Where are the Wishbone wires?

  #114 opened 2 years ago by shingarov
  2

• Generation fails because of wrong type of master and slave?

  #113 opened 2 years ago by shingarov
  1

• Request for info about daisy-chaining 5a75b boards with etherbone

  #103 opened 2 years ago by faeboli
  8

• Broadcast reception?

  #101 opened 2 years ago by sergachev
  4

• CI/Doc: Add tests for 32-bit/64-bit Datapath.

  #89 opened 3 years ago by enjoy-digital
  2

• LiteEthStream2UDPTX uses 0.0.0.0 port 0 when fifo_depth = None

  #69 opened 3 years ago by jevinskie
  1

• Rgmii_test.py not work rv901t

  #79 opened 3 years ago by apahm
  0

• `FullMemoryWE` leads to excessive blockram usage on ECP5

  #70 opened 3 years ago by david-sawatzke
  6

• LiteEth Linux driver: Discuss software interface, make sure it's convenient and will be stable over time.

  #60 opened 3 years ago by enjoy-digital
  2

• Sending ethernet frames using software

  #68 opened 3 years ago by BD00ley
  1

• Use LiteEth to add ethernet to an ECP5 with a PMOD

  #66 opened 3 years ago by cjearls
  2

• linux driver polling mode not init

  #62 opened 3 years ago by Chgavilana
  1

• very large LUT count on intel cyclone

  #63 opened 3 years ago by mczerski
  8

• Semicolon?

  #58 opened 3 years ago by davidcorrigan714
  1

• Feedback / Contribution / Support

  #44 opened 4 years ago by enjoy-digital
  0

• Problem with EtherboneRecordSender FIFO

  #55 opened 4 years ago by jedrzejboczar
  2

• Error building for Panologic platform ( Spartan 6 xc6slx150)

  #38 opened 4 years ago by skiphansen
  12

• Error when building with yosys for ECP5 with -retime

  #53 opened 4 years ago by rednaz1337
  1

• EtherBone data conversion issue

  #52 opened 4 years ago by jedrzejboczar
  5

• phy/ecp5rgmii: Incorrect parameters in DELAYF blocks

  #50 opened 4 years ago by gregdavill
  0

• ecp5rgmii does not meet timing closure

  #47 opened 4 years ago by festlv
  1

• Wishbone gen.py fails

  #45 opened 4 years ago by Xiretza
  0

• High area usage on Artix 7 due to buffers infered as distributed ram

  #43 opened 4 years ago by Dolu1990
  3

• Issues with GMII

  #37 opened 4 years ago by rjeschmi
  5

• phy/usrgmii.py: IDELAY_VALUE cannot exceed 1.25ns for Xilinx Ultrascale Devices.

  #29 opened 4 years ago by jersey99
  0

• Netboot issues with 1Gbps and low CPU frequency (<55MHz)

  #30 opened 4 years ago by enjoy-digital
  1

• IPv4 total length exceeds packet length (50 bytes)

  #25 opened 4 years ago by mithro
  6