Issues
- 0
Upper computer
#29 opened by woyuni - 0
- 4
Link not staying in U0 state
#15 opened by enjoy-digital - 1
trace file (vcd file) is failure?
#26 opened by cheungivan - 1
Breakout board missing drill file.
#24 opened by Shari2 - 1
usb A on both sides?
#25 opened by CarlFK - 1
LTSSM: fully implement it
#11 opened by enjoy-digital - 1
Link is for non-5G Versa board
#22 opened by osterwood - 2
ECP5 SerDes: Shorten RX initialization time / Get rid of BruteForceClockAligner
#18 opened by enjoy-digital - 10
ECP5: Validate SerDes at 5Gbps
#12 opened by enjoy-digital - 4
- 2
RX polarity detection / swap
#21 opened by enjoy-digital - 3
Add SKPInserter
#17 opened by enjoy-digital - 1
Use first/last delimiters on TX streams
#19 opened by enjoy-digital - 1
Synchronize Scrambler/Descrambler
#16 opened by enjoy-digital - 2
8B10B - Add invalid symbols detection
#5 opened by enjoy-digital - 2
- 1
Artix7: Fix rx_idle behavior for LFPS
#14 opened by enjoy-digital - 2
ECP5: Validate LFPS signaling
#13 opened by enjoy-digital - 1
Scrambling
#4 opened by enjoy-digital - 4
Define 7-Series/ECP5 Test Setup
#3 opened by enjoy-digital - 1
- 1
Add a quick README covering scope of project
#8 opened by mithro - 1
- 3
Make the repository public?
#9 opened by mithro - 0
Add a LICENSE file
#7 opened by mithro - 0
Links
#1 opened by enjoy-digital