Integrate Daisho Core and understand/fix limitations.
enjoy-digital opened this issue · 4 comments
A first integration of the Daisho USB3.0 core has been done: USB3 descriptors generation, adaptation of the interfaces for our USB3PIPE, integration of the verilog in the project and build scripts. The USB3PIPE + Daisho USB3.0 synthesis/place & route is working on Xilinx and Lattice devices. We now have to do more testing and understand/fix the limitations of the core. (for example, it seems the core is not handling backpressure: out_stall signal is on the link interface but not used, which will not be convenient since we'd like to use valid/ready signals of the LiteX's streams.)
Identified limitations:
- TX USB3 Link Layer is not handling back-pressure (there is an
out_stallsignal but it's not used). - TX USB3 Link Layer is not providing packets delimiters (needed for SKP insertion since it should not occurs inside a packet).
With 176617f, first/last delimiters are generated from out_active signal, this seem to fix SKP insertion in the middle of packets.
The lack of back pressure on the TX side has been compensated with a TX FIFO that absorbs the bursts from the core and retransmit data using the backpressure signals. This is probably enough for now to get the initialization working.
The work arounds implemented for the limitations allow the core to be correctly enumerated, which is enough for now for our experiment.