ECP5: Validate SerDes at 5Gbps
enjoy-digital opened this issue · 10 comments
Validate that we are able to run the SerDes at 5Gbps and check against a 7-series FPGA that TX/RX is working correctly.
ECP5 support has been added to LiteICLink with enjoy-digital/liteiclink@37d45f3 and enjoy-digital/liteiclink@bb5eabf. It has been validated at 2.5Gbps with a simple test design. We now need to test with a 7-series at the same linerate and then increase the linerate to 5Gbps.
5Gbps has been validated with LiteICLink example design and commit: enjoy-digital/liteiclink@39a41be (still with SMA loopback). We now need to test it against a Xilinx device.
The simple design has been validated between a KC705 and Versa ECP5, using SMA cables and PCIe (with a unmodified PCIe risers and the USB3 cable that does the TX/RX lanes swap).
The test designs are here:
https://github.com/enjoy-digital/liteiclink/tree/master/examples/transceiver
The next step is to test with USB3 and see if we able to send/receive packets.
The Beagle is able to see TSEQ/TS1 from the ECP5 but with some errors, but we have currently have large timing violations that could explain this:
Warning: Max frequency for clock '$glbnet$crg_clkout': 112.54 MHz (FAIL at 133.33 MHz)
Warning: Max frequency for clock '$glbnet$rx_clk': 180.18 MHz (FAIL at 250.00 MHz)
Warning: Max frequency for clock '$glbnet$tx_clk': 164.28 MHz (FAIL at 250.00 MHz)
So the next step is to optimize timings on ECP5.
@enjoy-digital Love those photos! :-)
@mithro :)
The timings have been improved and the Host now receives correctly the TSEQ/TS1 from the Versa ECP5. I still need to look at the RX path, but we should not be far from being able to use the Versa ECP5 for the dev.
I would really like to use USB 3.0 with the ECP5. Is there anything that you could would need help with? I'm not versed in migen but I do know digital design or could write documentation.
Also a question. It's possible to reach 5Gbps using a non 5G version of the ECP5? I thought the SERDES on those only supported upto 3Gbps.
@rowanG077: for now things are still very experimental, and not really in a working state (for USB3, 5Gbps SerDes is working) but this should be working in not too long.
The best for now to test with ECP5 is probably to use a Versa ECP5 and modify a PCIe riser cable like this: #3 (comment) Since getting 5Gbps is already tricky regarding timings with the 5G version, i'm not sure i would try with the non-5G versions.
If you want to review the actual code and/or improve the tests, your help is welcome.
The way we initialize the RX for ECP5 in the loopback demo is currently too slow for USB3 (using BruteForceClockAligner that checks for valid commas and resets the RX is errors are detected). To get USB3 working with ECP5 we'll need to get rid of the BruteForeClockAligner since the link RX path needs to be initialized when TSEQ are transmitted.
The ECP5 SerDes are working correctly at 5Gbps when tested in loopback and against a Xilinx device. The only remaining limitation is #18.