ECP5 SerDes: Shorten RX initialization time / Get rid of BruteForceClockAligner
enjoy-digital opened this issue · 2 comments
Due to RX initialization issue when testing the ECP5 SerDes in loopback mode or with another board, we are using a BruteForceClockAligner module to get RX working, but training is then not fast enough to be done during the USB3.0 TSEQ. We need to understand why it was needed and fix RX initialization properly to be able to test USB3.0 with ECP5 (TX is already working and TSEQ/TS1/TS2 are received correctly by the USB3.0 analyzer)
RX initialization has been reworked a bit (a RXInit module has been added) with enjoy-digital/liteiclink@7c3129d. The loopback example is working with it but this still needs to be tested with USB3.0.
enjoy-digital/liteiclink@7c3129d has tested and now allows the transceiver to be initialized fast enough for USB3 (during TSEQ).