enjoy-digital/litedram

Issues

• Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO

  #358 opened a month ago by epsilon537
  2

• Adding support to gowin phys in litedram.gen?

  #357 opened 2 months ago by linhz0hz
  0

• LiteDRAMDMAWriter sinks data when not enabled

  #356 opened 2 months ago by DaveBerkeley
  2

• LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

  #344 opened 10 months ago by dinaabdelbaky
  1

• Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file,

  #355 opened 3 months ago by fontamsoc
  0

• GENDDRPHY support?

  #353 opened 5 months ago by rhgndf
  0

• litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)

  #349 opened 8 months ago by jersey99
  5

• DE10-Lite Memory initialization failed

  #347 opened 9 months ago by LearnShareAlways
  0

• Underclocking DRAM controler to increase access time

  #346 opened 10 months ago by denishoornaert
  0

• LiteDRAM core targeting DDR3 issues activate command twice for a write operation

  #345 opened 10 months ago by dinaabdelbaky
  0

• Axi port write data error

  #342 opened a year ago by Yuxin-Yu
  8

• Carrying out the LiteDRAM standalone core initialization manually, through wishbone ctrl interface

  #327 opened a year ago by dinaabdelbaky
  5

• Is it possible to adjust burst-length in order to widen data path ?

  #339 opened a year ago by fontamsoc
  0

• DDR3 Memory on Kintex7 325T based board randomly fails

  #285 opened 2 years ago by tongchen126
  48

• wb_ctrl ports of ECP5 litedram_core generated for OrangeCrab02-25F failing when user_ports is native

  #338 opened a year ago by fontamsoc
  0

• LiteDRAMDMAWriter cannot write accurate data to a specific address?

  #336 opened a year ago by Prigana
  0

• AxSIZE mismatch?

  #334 opened a year ago by TheZoq2
  1

• ulx3s example does not work

  #329 opened a year ago by TheZoq2
  3

• Setting for user_clk

  #333 opened a year ago by ztachip
  1

• Generate liteDRAM verilog file

  #331 opened a year ago by ztachip
  4

• DDR4 reads without DQS at high speeds?

  #328 opened a year ago by alexey-morozov
  1

• Simulation issue, Arty S7 (Beginner)

  #309 opened 2 years ago by TheAnimatrix
  9

• --top-module 'sim' was not found in the design

  #325 opened a year ago by CarrolXC
  5

• Need Help Generating Verilog DRAM controller, while maininting module hiraerachies.

  #324 opened a year ago by dinaabdelbaky
  1

• DMA AXI BUG

  #318 opened a year ago by mohammadshahidzade
  1

• Corresponding verilog testbench for ASIC

  #317 opened a year ago by CarrolXC
  1

• submodules verilog

  #316 opened a year ago by CarrolXC
  2

• sdram_init() vs. init_sequence()

  #315 opened a year ago by epsilon537
  0

• Problem with adding new LPDDR module: MT46H128M16

  #310 opened 2 years ago by cklarhorst
  1

• Typical litedram-L2 port sizes

  #312 opened 2 years ago by bala122
  0

• Help generating DDR3 Verilog module for Digilent NexysVideo Artix-7 FPGA

  #281 opened 3 years ago by tambewilliam
  3

• QuarterRateGENSDRPHY

  #308 opened 2 years ago by machdyne
  2

• New to LiteDRAM

  #307 opened 2 years ago by FATHY174
  2

• Why are CL and CWL not included as speedgrade parameters in the module class?

  #306 opened 2 years ago by jaccharrison
  1

• LiteDRAM USPDDRPHY unable to meet DDR4 timing requirements?

  #303 opened 2 years ago by jaccharrison
  8

• Unable to run Litedram on Digilent Genesys2

  #297 opened 2 years ago by fontamsoc
  6

• DDR4 Memtest Failed

  #305 opened 2 years ago by zhbeiluo
  3

• Strategy steering: Best way to stream data into a custom accelerator when litedram is being used inside Litex SoC?

  #304 opened 2 years ago by francis2tm
  4

• Help creating verilog module to go from Wishbone4 to Litedram native port

  #298 opened 2 years ago by fontamsoc
  1

• ULX4M DM signal is not connected to DQS group

  #299 opened 2 years ago by goran-mahovlic
  2

• memtest fails on arty depending on read leveling outcome

  #296 opened 2 years ago by acomodi
  3

• Initialization failed on Artix after e5e3b6c

  #293 opened 2 years ago by kaolpr
  5

• Possible to Create Software Initialization File Without Regenerating Core?

  #288 opened 2 years ago by jacquuelinee-b
  1

• Figure out how to hook LiteDRAM to the WDDR PHY

  #265 opened 3 years ago by mithro
  1

• generate user interface

  #289 opened 2 years ago by 12ff7a6
  1

• LDDR5 Support

  #291 opened 2 years ago by pjattke
  2

• The MAX sys_clk_freq supported of DDR4

  #272 opened 3 years ago by uxilinx
  1

• Changes to tREFI ignored

  #264 opened 3 years ago by SLongofono
  5

• litedram does not use full address space?

  #263 opened 3 years ago by Aljeshka
  7

• sdram.c:39:37: error: static declaration of 'cdelay' follows non-static declaration

  #262 opened 3 years ago by hansfbaier
  1