sdram.c:39:37: error: static declaration of 'cdelay' follows non-static declaration
hansfbaier opened this issue · 1 comments
hansfbaier commented
python3 litex_boards/targets/linsn_rv901t.py
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-07-10 08:16:16)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc6slx16-2-ftg256.
INFO:SoC:System clock: 75.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:S6PLL:Creating S6PLL, speedgrade -2.
INFO:S6PLL:Registering Single Ended ClkIn of 25.00MHz.
INFO:S6PLL:Creating ClkOut0 sys of 75.00MHz (+-10000.00ppm).
INFO:S6PLL:Creating ClkOut1 sys_ps of 75.00MHz (+-10000.00ppm).
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00800000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:S6PLL:Config:
divclk_divide : 1
clkout0_freq : 75.00MHz
clkout0_divide: 13
clkout0_phase : 0.00°
clkout1_freq : 75.00MHz
clkout1_divide: 13
clkout1_phase : 90.00°
vco : 975.00MHz
clkfbout_mult : 39
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:leds CSR allocated at Location 2.
INFO:SoCCSRHandler:sdram CSR allocated at Location 3.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 4.
INFO:SoCCSRHandler:uart CSR allocated at Location 5.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False
sram : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x00800000, Mode: RW, Cached: True Linker: False
csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (4)
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (6)
- ctrl : 0
- identifier_mem : 1
- leds : 2
- sdram : 3
- timer0 : 4
- uart : 5
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
make: Entering directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/libcompiler_rt'
CC umodsi3.o
CC udivsi3.o
CC divsi3.o
CC modsi3.o
CC comparesf2.o
/devel/riscv/litex-root/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparesf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
FNALIAS(__cmpsf2, __lesf2);
^~~~~~~
CC comparedf2.o
/devel/riscv/litex-root/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparedf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
FNALIAS(__cmpdf2, __ledf2);
^~~~~~~
CC negsf2.o
CC negdf2.o
CC addsf3.o
CC subsf3.o
CC mulsf3.o
CC divsf3.o
CC lshrdi3.o
CC muldi3.o
CC divdi3.o
CC ashldi3.o
CC ashrdi3.o
CC udivmoddi4.o
CC floatsisf.o
CC floatunsisf.o
CC fixsfsi.o
CC fixdfdi.o
CC fixunssfsi.o
CC fixunsdfdi.o
CC adddf3.o
CC subdf3.o
CC muldf3.o
CC divdf3.o
CC floatsidf.o
CC floatunsidf.o
CC floatdidf.o
CC fixdfsi.o
CC fixunsdfsi.o
CC clzsi2.o
CC ctzsi2.o
CC udivdi3.o
CC umoddi3.o
CC moddi3.o
CC ucmpdi2.o
CC mulsi3.o
AR libcompiler_rt.a
make: Leaving directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/libcompiler_rt'
make: Entering directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/libbase'
CC crt0.o
CC exception.o
CC libc.o
CC errno.o
CC crc16.o
CC crc32.o
CC console.o
CC system.o
CC id.o
CC uart.o
CC time.o
CC qsort.o
CC strtod.o
CC spiflash.o
CC strcasecmp.o
CC i2c.o
CC div64.o
CC progress.o
CC memtest.o
CC sim_debug.o
CC vsnprintf.o
AR libbase.a
CC vsnprintf-nofloat.o
AR libbase-nofloat.a
make: Leaving directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/libbase'
make: Entering directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/libfatfs'
CC ffunicode.o
CC ff.o
AR libfatfs.a
make: Leaving directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/libfatfs'
make: Entering directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/liblitespi'
CC spiflash.o
AR liblitespi.a
make: Leaving directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/liblitespi'
make: Entering directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/liblitedram'
CC sdram.o
/home/jack/.local/lib/python3.8/site-packages/litex-0.0.0-py3.8.egg/litex/soc/software/liblitedram/sdram.c:39:37: error: static declaration of 'cdelay' follows non-static declaration
__attribute__((unused)) static void cdelay(int i)
^~~~~~
In file included from /home/jack/.local/lib/python3.8/site-packages/litex-0.0.0-py3.8.egg/litex/soc/software/liblitedram/sdram.c:20:
/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/include/generated/sdram_phy.h:28:6: note: previous declaration of 'cdelay' was here
void cdelay(int i);
^~~~~~
make: *** [/home/jack/.local/lib/python3.8/site-packages/litex-0.0.0-py3.8.egg/litex/soc/software/liblitedram/Makefile:15: sdram.o] Error 1
make: Leaving directory '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/liblitedram'
Traceback (most recent call last):
File "litex_boards/targets/linsn_rv901t.py", line 111, in <module>
main()
File "litex_boards/targets/linsn_rv901t.py", line 104, in main
builder.build(run=args.build)
File "/home/jack/.local/lib/python3.8/site-packages/litex-0.0.0-py3.8.egg/litex/soc/integration/builder.py", line 270, in build
self._generate_rom_software(compile_bios=use_bios)
File "/home/jack/.local/lib/python3.8/site-packages/litex-0.0.0-py3.8.egg/litex/soc/integration/builder.py", line 230, in _generate_rom_software
subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
File "/usr/lib/python3.8/subprocess.py", line 364, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['make', '-C', '/devel/riscv/litex-root/litex-boards/build/linsn_rv901t/software/liblitedram', '-f', '/home/jack/.local/lib/python3.8/site-packages/litex-0.0.0-py3.8.egg/litex/soc/software/liblitedram/Makefile']' returned non-zero exit status 2.
hansfbaier commented
invalid. this was using an old local litex installation