LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

Question

LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

Opened this issue a year ago · 1 comments

Hi,
I have generated LiteDRAM core targeting DDR3 with the configuration in Fig1. I have noticed for a read command issued from the AXI interface the rd_data is returned in the rd_data of native interface, not the AXI interface Fig2

Answer 1 · 2024-04-25T07:10:04.000Z

@dinaabdelbaky
Hello, can you read and write AXI_Litedram normally?
I encountered the same type of problem as #342 （Axi port write data error #342）
If it's convenient, leave an email （bumianzhe@126.com）to communicate, thank you.