enjoy-digital/liteiclink

Issues

• GTPQuadPLL: refclk is connected to GTREFCLK0 by default

  #17 opened a month ago by hansfbaier
  2

• GTPQuadPLL: refclk is connected to GTREFCLK0 by default

  #18 opened a month ago by hansfbaier
  1

• [Feature request] adding support of Universal Chiplet Interconnect Express (UCIe)

  #15 opened 10 months ago by ohault
  0

• GTHE3: Verify QPLL operation on KCU105.

  #5 opened a year ago by enjoy-digital
  3

• Build for versa_ecp5.py serdes sample fails

  #4 opened 3 years ago by goran-mahovlic
  4

• Feedback / Contribution / Support

  #1 opened 4 years ago by enjoy-digital
  0

• [question] Loopback test with serwb

  #3 opened 4 years ago by kamejoko80
  9

• Nexys SerWB example not building

  #2 opened 4 years ago by rlipperts
  4