enjoy-digital/litesata

Issues

• Improve Ultrascale(+) PHYs naming.

  #32 opened 6 months ago by enjoy-digital
  0

• Working linux driver

  #31 opened 7 months ago by cyntem
  1

• LiteSATA Bench not initializing on Nexys Video

  #28 opened 10 months ago by md-raz
  0

• Add/Finish ECP5 support.

  #27 opened a year ago by enjoy-digital
  3

• Add IRQs to notify SATA connect/disconnect and end of DMAs

  #21 opened 4 years ago by enjoy-digital
  0

• how is the serial port used?

  #24 opened 3 years ago by Quenii
  1

• Feedback / Contribution / Support

  #17 opened 4 years ago by enjoy-digital
  0

• Switch PHYs to LiteICLink

  #19 opened 4 years ago by enjoy-digital
  2

• Understand why set_reset_less can't be used in streams.

  #23 opened 4 years ago by enjoy-digital
  0

• Artix7: Allow use without 150MHz refclk.

  #22 opened 4 years ago by enjoy-digital
  1

• Add DMA frontend

  #20 opened 4 years ago by enjoy-digital
  1

• Add Artix7 support

  #16 opened 4 years ago by enjoy-digital
  2

• Zero delay oscillations in Vivado XSIM simulation

  #18 opened 4 years ago by mik1234mc
  3

• reported broken with LiteX > 6a7604cbb06454813541bc308791e90e051555af

  #11 opened 6 years ago by enjoy-digital
  1

• Need to repeat last primitive after an ALIGN when sending CONT

  #4 opened 8 years ago by enjoy-digital
  1

• adapt simulations to new simulator

  #9 opened 8 years ago by enjoy-digital
  2