clock_cls?
Closed this issue · 2 comments
AnttiLukats commented
it seems that the following line limits the use of the litevideo for only XC6 XC7 FPGA's?
self.submodules.clocking = clocking_cls[family](pads, external_clocking)
enjoy-digital commented
Indeed, the others FPGA families are not currently supported.
enjoy-digital commented
Closing since that's the only supported FPGA families (for now) and specified in the README.