© 2023 Tutor Nelson Salvador, students Shawn Rodrigues and Pablo Aravena, Advanced Center for Electrical and Electronic Engeneering (AC3E), Universidad Tecnica Federico Santa Maria (USM), Valparaiso, Chile
AES is a symmetric encryption standard handling 128-bit data blocks and key sizes of 128, 192, or 256 bits. It employs rounds of operations including SubBytes, ShiftRows, MixColumns, and AddRoundKey, and has various hardware implementations in ASICs and FPGAs, with design strategies focusing on low power, compactness, and key size flexibility. One approach uses 8-bit data paths and parallel operations to reduce cycle counts. The AES core consists of components like byte permutation, MixColumns, S-boxes (duplicated), and key expansion. Overall, AES is versatile and adaptable for different hardware contexts.
The project is based on on ChengluJin's github on "8-bit_datapath_AES", where AES-128 is used in ECB-mode only for the encryption part, with some modifications in order to work with the expected IOs and format for TinyTapeout. In this version of the AES implementation, both inputs (key and data) are entered byte-to-byte on each clock-rise, and null bytes of data are sent to the output until a flag is set internally in order to drive the output pins with the encrypted data.
Please see the instructions for:
When you edit the info.yaml to choose a different ID, the GitHub Action will fetch the digital netlist of your design from Wokwi.
After that, the action uses the open source ASIC tool called OpenLane to build the files needed to fabricate an ASIC.
- Submit your design to the next shuttle on the website, the closing date is 8th September.
- Share your GDS on Twitter, tag it #tinytapeout and link me!