Zeno
sbt > run asm/hello.s
Tests
sbt test
Verilog
First install Yosys:
brew install yosys
To check the synthesized result:
yosys -S verilog/filter.v
With FPGA as target:
yosys -p synth_xilinx -S verilog/adder.v
liufengyun/zeno-deprecated
The DSL based on implicit state machines as in LCTES 22 (deprecated, newer version is coming)
Scala