liuhangr's Stars
ultraembedded/core_jpeg
High throughput JPEG decoder in Verilog for FPGA
ultralytics/yolov5
YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite
open-mmlab/mmyolo
OpenMMLab YOLO series toolbox and benchmark. Implemented RTMDet, RTMDet-Rotated,YOLOv5, YOLOv6, YOLOv7, YOLOv8,YOLOX, PPYOLOE, etc.
argusswift/YOLOv4-pytorch
This is a pytorch repository of YOLOv4, attentive YOLOv4 and mobilenet YOLOv4 with PASCAL VOC and COCO
lulinchen/cnn_open
A hardware implementation of CNN, written by Verilog and synthesized on FPGA
OldRepoPreservation/mpeg2fpga
An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.
junegunn/vim-plug
:hibiscus: Minimalist Vim Plugin Manager
vim/vim
The official Vim repository
HonkW93/automatic-verilog
automatic-verilog based on vimscript
WillGreen/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
projf/display_controller
FPGA display controller with support for VGA, DVI, and HDMI.
ronitrex/ARMLEG
Multi-cycle pipelined ARM-LEGv8 CPU with Forwarding and Hazard Detection.
nxbyte/Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
nxbyte/ARM-LEGv8
Verilog Implementation of an ARM LEGv8 CPU
muhammadaldacher/Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Amsterdam-Data-Collective/adc-pipeline
A pipeline for a structured way of working