Verilog HDL Implementation of well known old game LIFE in FPGA Altera MAX10. CAD: Altera Quartus Prime Lite. FPGA Board marsohod3. Now supports 64x32 cells. Initial field seed over serial port: just send TXT file like ./some_life/gosper50.txt to board. Serial settings: 115200, 8bit, 1stop, no parity. Field display over HDMI port 1280x720. Board description: https://marsohod.org/plata-marsokhod3
View video demo at: https://youtu.be/1fjvGrfTt_w