[top] FPGA hangs I2C line to ADN4604ASVZ

[lerwys]

This issue was reported by Piotr Miedzik (@qermit) and later by Henrique Silva (@henrique-silva).

Problem: There is only short window when ADN may be reconfigured.
This is FPGA booting time, after switching power on and before FPGA bitstream was uploaded to fpga.

ADN4604ASVZ is using P3V3 voltage (+3.3V_CLKSW to be precise)
Signal direction inside SN74AVC8T245RHLR (ic41???) is controlled with PVADJ2.
During power sequence direction is changing.
While fpga is booting outputs are in high state until end of this procedure.
After successful upload behavior of unused pins depends default pin policy.
In this case all unused pins goes down thereby it's impossible to update ADN configuration anymore (CLK_UPDATEn stays low)

In general it's not required to change clock configuration, however, in some cases it's good to have such option (e.g during tests)

Solution:

Due to lack of VADJ2_CLK_UPDATEN definition (U24 in AFCv2 and AFCv3)
It's impossible to update clock matrix output configuration (ADN4604) with MMC
After fpga firmware upload UPDATEn pin stays always low.

Something like this is required:
set_property PACKAGE_PIN U24 [get_ports vadj2_clk_updaten_io]
set_property IOSTANDARD LVCMOS25 [get_ports vadj2_clk_updaten_io]
set_property PULLUP true [get_ports vadj2_clk_updaten_io]