lnls-dig/bpm-gw

Issues

• Incorrect comments in the FMC ADCs SPI interface

  #110 opened 2 months ago by augustofg
  0

• [orbit_intlk] - Expose minimum sum comparator output

  #98 opened 3 months ago by mmdonatti
  1

• [Interlock] Improvements

  #83 opened 5 months ago by lerwys
  1

• [pcie_core] Cannot access DDR data from high address

  #45 opened 10 years ago by lerwys
  2

• [pcie] Supurious PCIe link down event

  #73 opened 2 years ago by lerwys
  1

• Add MONIT1 data rate to Post-Mortem acquisition

  #84 opened 3 years ago by lerwys
  0

• [wb_fmcpico1m_4ch] Raw data might cross 0 with small signals causing wrong interpretation

  #82 opened 4 years ago by lerwys
  0

• [MONIT1/MONIT tag delay] delays are applied as "ADC clock cycles" granularity

  #81 opened 4 years ago by lerwys
  0

• [FOFB sync] FOFB sync only works when switching is in "switching" mode

  #80 opened 4 years ago by lerwys
  0

• [wb_fmcpico1m_4ch] Aquisition clock must be synchonized with machine clock

  #79 opened 4 years ago by lerwys
  0

• Allow simulataneous range selection on XBPM gateware

  #78 opened 5 years ago by danielot
  0

• [acq_core] Triggered acquisiton does not support post_samples = 0

  #62 opened 6 years ago by lerwys
  3

• [system] Some FMC-related modules (acq, fmc250m_4ch) do not reset via PCIe

  #58 opened 6 years ago by lerwys
  1

• [fmc130m] Top .ucf .xdc files for FMC130M are misleading

  #53 opened 9 years ago by lerwys
  0

• [dbe_common] [clock_driver] Reset synch MAX_FANOUT attribute must be reviewed

  #47 opened 6 years ago by aylons
  1

• [pcie_core] [dbe_bpm_dsp] XDC files references nets Vivado can't find

  #46 opened 6 years ago by aylons
  1

• [top] Add remaining DSP signal paths to acquisition core

  #42 opened 6 years ago by lerwys
  1

• [wb_acq_core] Negative delay values breaks acquisition

  #77 opened 6 years ago by lerwys
  0

• [acq_core] Acquiring "mix" datapath stalls acquisition core

  #60 opened 6 years ago by lerwys
  1

• [acq_core] Multi-shots acquisition is currently not working

  #61 opened 6 years ago by lerwys
  1

• [position_calc] Data masking does not work all the time

  #76 opened 6 years ago by lerwys
  1

• [acq_core] Jittery triggered acquisition

  #75 opened 6 years ago by lerwys
  2

• [wb_trigger_iface] Module not synched with receiving trigger/clock from MLVDS bus

  #70 opened 6 years ago by lerwys
  0

• [wb_trigger] Add enable input in each logical trigger

  #74 opened 6 years ago by danielot
  0

• [si57x] Changing Si57x frequency reset some cores

  #72 opened 7 years ago by lerwys
  1

• [acq_core] More options for data-driven trigger

  #71 opened 7 years ago by danielot
  0

• [wb_trigger_iface] Missing pulse extender check if length = 0

  #69 opened 7 years ago by lerwys
  0

• [top] Implement simple hearbeat scheme with AFC front panel leds

  #50 opened 7 years ago by lerwys
  1

• [wb_acq_core] Fix crossing of control registers to ext_clk_i

  #41 opened 7 years ago by lerwys
  1

• [acq_core] Mixed acquisition when post-mortem is on

  #68 opened 7 years ago by lerwys
  0

• [acq_core] Eventually acquisition starts at a misaligned sample

  #64 opened 8 years ago by lerwys
  0

• [fmc250m_4ch] Expose ADC delay functions enhancement

  #65 opened 8 years ago by lerwys
  0

• [dbe_bpm2] pll_status_i unconnected

  #66 opened 8 years ago by lerwys
  0

• [trigger] Trigger IFACE has typo on register assingment

  #67 opened 8 years ago by lerwys
  0

• [wb_trigger] Module not flexible enough

  #56 opened 8 years ago by lerwys
  0

• [wb_acq_core] Mixed data when aborting acquisition

  #57 opened 8 years ago by lerwys
  0

• [top] FPGA hangs I2C line to ADN4604ASVZ

  #59 opened 8 years ago by lerwys
  0

• [flash_loader] Implement Flash Loader via PCIe/Wishbone

  #55 opened 9 years ago by lerwys
  0

• Monitoring datapath returns invalid data

  #54 opened 9 years ago by danielot
  0

• [wb_acq_core] Cannot acquire less than f_log2(<output data width>/<input channel data width>) samples

  #48 opened 9 years ago by lerwys
  0

• [wb_acq_core] On trigger acquisitions we can have a sample not belonging to the correct transaction

  #52 opened 9 years ago by lerwys
  1

• [ddr3_core] Missing Vivado project file

  #44 opened 9 years ago by lerwys
  1

• [wb_acq_core] Core can hang the DDR3 grant line forever

  #36 opened 9 years ago by lerwys
  1

• [vivado_project] AXI Interconnect BPM is not generated as VHDL and simulation fails

  #51 opened 9 years ago by lerwys
  0

• [top,syn] sanitize project folders

  #49 opened 9 years ago by lerwys
  1

• [wb_acq_core:acq_fc_fifo] Optimize Flow Control Buffer

  #40 opened 9 years ago by lerwys
  0

• [wb_acq_core] Check lmt_curr_chan_id signal and its use

  #43 opened 10 years ago by lerwys
  0

• [wb_fmc130m_4ch] Each 77 samples is repeated on acquisition

  #38 opened 10 years ago by lerwys
  0

• [wb_acq_core] Acquisition FIFO gets full when ext_clk_i is lower than fs_clk_i

  #37 opened 10 years ago by lerwys
  0

• [wb_fmc130m_4ch] ADC clock current delay value not used

  #39 opened 10 years ago by lerwys
  0