[acq_core] Acquiring "mix" datapath stalls acquisition core

[lerwys]

Problem: Acquiring from "mix" datapath stall firmware. The total "mix" bandwidth is 4 bytes per atom * 4 atoms (channels) * 210MHz ~ 3360 MB/s. However, the total DDR3 bandwidth is 4 bytes (32 bit interface) * 800 MHz ~ 3200 MB/s.

This poses an impossible problem to solve for this "mix" bandwidth, as we can only acquire as many data samples as the intermediate acquisition FIFO size (around 1024 samples).

Even with this limitation, the acquisition core must not stall and deny receiving new acquisition.

Solution: Restructure "mix" bandwidth to cope with the 3200 MB/s limitation and do not stall acquisition core

[lerwys]

No way of coping with the "mixer" bandwidth. It's just too much for DDR3 with Xilinx artix7. There is an error flag on software to warn user of this when it happens