Gateware cores for providing infrastructure in building complex systems.
The cores available here could be categorized into the following:
Bus master cores comprising cores which bridges between a node (CPU, another board, etc), to a SoC Bus (Wishbone, AXI, etc) such as: Ethernet, PCIe, UART.
Board/CI interfaces comprising cores to communicate to an external chip/board (ADC mezzanine, Trigger mezzanine, etc)
General cores comprising cores used to group a common functionality, such: reset synchronizers.