Pinned Repositories
Facebook_Online_Notifier
MIPS
A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
RISC-processor
Simple RISC processor written in verilog
Verilog-MIPSProcessor
Full implementation of a modifed MIPS processor in Verilog.
losersiitr's Repositories
losersiitr/Facebook_Online_Notifier
losersiitr/MIPS
A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
losersiitr/RISC-processor
Simple RISC processor written in verilog
losersiitr/Verilog-MIPSProcessor
Full implementation of a modifed MIPS processor in Verilog.