Layout of this repository:
- constrs constraint files
- doc documentations and figures
- hdl verilog source files
- header verilog header files
- sim testbench files for simulation
The available hardware resources on Xilinx ZCU111 platform are:
LUT | FF | BRAM | DSP |
---|---|---|---|
425,280 | 850,560 | 1,080 | 4,272 |
Following results are generated by Vivado version 2020.2. The FPGA resource usage of 1 PE (running at 600MHz) is:
LUT | FF | BRAM | DSP |
---|---|---|---|
721 | 615 | 2.0 | 4 |
The FPGA resource usage of an 32-PE overlay (running at 590MHz) is:
LUT | FF | BRAM | DSP |
---|---|---|---|
26321 | 23887 | 66.0 | 128 |
The FPGA resource usage of an 64-PE overlay (running at 560MHz) is:
LUT | FF | BRAM | DSP |
---|---|---|---|
49615 | 45599 | 130.0 | 256 |
The FPGA resource usage of an 128-PE overlay (running at 530MHz) is:
LUT | FF | BRAM | DSP |
---|---|---|---|
96259 | 88239 | 258.0 | 512 |
22.6% | 10.4% | 23.9% | 12.0% |
The 32-bit shift register logic (SRL) can be implemented by FFs or LUTs:
LUT | FF | |
---|---|---|
Register-based | 0 | 1,024 |
SLICEM-based | 32 | 64 |
DSP48E2 configuration:
Operation | INMODE | OPMODE | ALUMODE |
---|---|---|---|
ADD | 00000 | 000110011 | 0000 |
SUB | 00000 | 000110011 | 0001 |
MUL | 00000 | 000000101 | 0000 |
MULADD | 00000 | 000110101 | 0000 |
MULSUB | 00000 | 000110101 | 0001 |
COMPARE | 00000 | 000110011 | 1100 |