This project is a university exercise done at Nantes University in 3rd year of engineering cycle specialized Electrical and Digital Technology department.
The objective of this mini-project is to design a microprocessor-based system by reusing basic component blocks. The first part of the project consists in reusing the code of a simple RAM described in VHDL by making it generic. Then, we have to create a block containing several instances of this RAM and a decoder to access it. Finally, the last part of the project consists in integrating this memory block into a system comprising a processor described in Verilog. The objectives of this lab are to introduce the students to the notions of genericity and IP reuse, while allowing them to get back in touch with VHDL and to discover Verilog. Moreover, they will be led to integrate the various components between them to produce a usable global module.
The report is available in the main folder. To run the source files .vhd and .vs we used GHDL and Verilator.