lovisXII
CPU designer. Former master SESI (IT systems) in Jussieu. Holder of a License degree in Physics.
Pinned Repositories
Alliance_installer
ARM_CPU
Description of a ARM V2 architecture in vhdl
atmega328p
Float_emulation
Small attend to emulate float operation using integer
Klaw_CORE
Netlist-viewer
This is a Netlist viewer using c++ and Qt4
NMV
RiVer_core
RiVer_SoC
Description of a RISC-V architecture based on MIPS 3000
RiVer_SS2
A super-scalar Core based on RISCV in systemC
lovisXII's Repositories
lovisXII/RiVer_SoC
Description of a RISC-V architecture based on MIPS 3000
lovisXII/RiVer_SS2
A super-scalar Core based on RISCV in systemC
lovisXII/Alliance_installer
lovisXII/ARM_CPU
Description of a ARM V2 architecture in vhdl
lovisXII/Klaw_CORE
lovisXII/RiVer_core
lovisXII/atmega328p
lovisXII/Float_emulation
Small attend to emulate float operation using integer
lovisXII/Netlist-viewer
This is a Netlist viewer using c++ and Qt4
lovisXII/NMV
lovisXII/RISCV_tests
Assembly file allowing you to test any RISCV implementation
lovisXII/Simulateur_impots_revenus
Ce git est un simulateur du taux d'impositions sur le revenu. Il met en parallèle l'impôt a 5 tranche avec celui a 15 (propose par le nfp).