Pinned Repositories
.cfg
.tmux
.vim
antlr_swing
ar-translator
auto_pr_comments_from_forks
Shows how to make GitHub actions post PR comments from forked repositories
bazel-verilog-test
Testing verilog build rules from https://github.com/hdl/bazel_rules_hdl
ble-gateway
ble-node-bme280
LaparoTalker
Program komunikujący się z trenażerem firmy Laparo
lpawelcz's Repositories
lpawelcz/ar-translator
lpawelcz/.cfg
lpawelcz/.tmux
lpawelcz/.vim
lpawelcz/antlr_swing
lpawelcz/auto_pr_comments_from_forks
Shows how to make GitHub actions post PR comments from forked repositories
lpawelcz/bazel-verilog-test
Testing verilog build rules from https://github.com/hdl/bazel_rules_hdl
lpawelcz/ble-gateway
lpawelcz/ble-node-bme280
lpawelcz/buildx
Docker CLI plugin for extended build capabilities with BuildKit
lpawelcz/CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with using custom opcodes to accelerating TensorFlow Lite for Microcontroller (TFLM).
lpawelcz/comment-test
lpawelcz/dl-picture-colorization
lpawelcz/litex
Build your hardware, easily!
lpawelcz/MIASI
lpawelcz/miasi-eclipse
lpawelcz/node_pcb
Kicad design - ESP32 node board
lpawelcz/picofoxy
Pipelined In-order Core for Artix-7 Arty-35T board
lpawelcz/PolarPro3
QuickLogic device PolarPro3 Information
lpawelcz/ppiwd_server
lpawelcz/python-netacad
lpawelcz/pythondata-cpu-vexriscv
Python module containing verilog files for vexriscv cpu (for use with LiteX).
lpawelcz/quicklogic-fasm
lpawelcz/read-binary
lpawelcz/scripts
my utilities
lpawelcz/single_chan_pkt_fwd
Single Channel LoRaWAN Gateway
lpawelcz/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
lpawelcz/vim_my_plugins
lpawelcz/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
lpawelcz/yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.